-- $Id: $
-- File name:   tb_DECODE.vhd
-- Created:     10/5/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_DECODE is
generic (Period : Time := 83.34 ns);
end tb_DECODE;

architecture TEST of tb_DECODE is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component DECODE
    PORT(
         CLK : in std_logic;
         RST_N : in std_logic;
         D_PLUS : in std_logic;
         SHIFT_ENABLE : in std_logic;
         EOP : in std_logic;
         D_ORIG : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal CLK : std_logic;
  signal RST_N : std_logic;
  signal D_PLUS : std_logic;
  signal SHIFT_ENABLE : std_logic;
  signal EOP : std_logic;
  signal D_ORIG : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_tmp: std_logic := '0';
begin
  CLK_tmp := not CLK_tmp;
  CLK <= CLK_tmp;
  wait for Period/2;
end process;

  DUT: DECODE port map(
                CLK => CLK,
                RST_N => RST_N,
                D_PLUS => D_PLUS,
                SHIFT_ENABLE => SHIFT_ENABLE,
                EOP => EOP,
                D_ORIG => D_ORIG
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

--     RST_N <= 
--     D_PLUS <= 
--     SHIFT_ENABLE <= 
--     EOP <= 

-- -- --     RST_N <= '1';
-- -- --     D_PLUS <= '0';
-- -- --     SHIFT_ENABLE <='0';
-- -- --     EOP <= '0';
-- -- -- 
-- -- --     wait for period;
-- -- --     RST_N <= '0';
-- -- --     wait for period;
-- -- --     RST_N <= '1';
-- -- -- 
-- -- --     wait for period;
-- -- --     SHIFT_ENABLE <='1';
-- -- --     D_PLUS <= '1';
-- -- --     wait for period;
-- -- --     SHIFT_ENABLE <='0';
-- -- --     D_PLUS <= '0';
-- -- --     wait for period;

--     wait for period;
--     SHIFT_ENABLE <='1';
--     wait for period;
--     --SHIFT_ENABLE <='0';


    --data to be sent in 1010 0011
--     D_PLUS <= '1';
--     wait for period;
--     D_PLUS <= '1';
--     wait for period;
--     D_PLUS <= '0';
--     wait for period;
--     D_PLUS <= '0';
--     wait for period;
-- 
--     D_PLUS <= '0';
--     wait for period;
--     D_PLUS <= '1';
--     wait for period;
--     D_PLUS <= '0';
--     wait for period;
--     D_PLUS <= '1';

-- -- --     wait for 4*period;
-- -- --     EOP <= '1';

    EOP<='0';
    RST_N <= '1';
    wait for 4*period;

    RST_N <= '0';
    wait for period;

    D_PLUS <= '1';
    SHIFT_ENABLE <='0';
    wait for period;
    RST_N <= '1';
    wait for period;
    SHIFT_ENABLE <='1';
    wait for period;

--////////////////////////

    D_PLUS <= '1';
    SHIFT_ENABLE <='0';
    wait for period;
    D_PLUS <= '0';
    wait for period;
    D_PLUS <= '1';
    wait for period;
    D_PLUS <= '0';
    wait for period;

    SHIFT_ENABLE <='1';

    D_PLUS <= '0';
    wait for period;
    SHIFT_ENABLE <='0';
    D_PLUS <= '1';
    wait for period;
    D_PLUS <= '0';
    wait for period;

    SHIFT_ENABLE <='1';
    D_PLUS <= '1';


    wait for 4*period;
    RST_N <= '0';
    SHIFT_ENABLE <='0';
    wait;



   wait;

  end process;
end TEST;





